With the growth in IC manufacturing costs, an understanding of the effects of more sophisticated logic synthesis techniques is essential for future advances in both the theory and implementation of automatic circuit synthesis. This article is a summary of the research conducted at Carnegie Mellon and McGill Universities attempting to explain the impact of retiming on the testability of sequential logic circuits. A number of interesting findings are discussed, including a novel test preservation theorem which suggests a powerful way to decrease the test generation cost of retimed circuits, and a newly recognized circuit attribute which permits the complexity of structural, sequential automatic test pattern generation (ATPG) to be viewed from a new perspective.