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Synthesizing Circuits with Implicit Testability Constraints
Summer 1995 (vol. 12 no. 2)
pp. 16-23

The goal of test synthesis is to create a circuit which is completely testable under a design-for-test (DFT) methodology while meeting performance and area requirements. It includes such steps as testability design rule checking and automated repair of identified violations. Potential violations include clock and asynchronous circuitry which do not operate in a manner consistent with the chosen methodology and tools.

This article discusses the concept of test synthesis constraints, which embody the conditions under which the circuit must operate in order to be fully testable. Based on these constraints, the network is transformed to repair corresponding rule violations using algorithms similar to those of automatic test pattern generation.

The design process is optimized by incorporating test synthesis into front-end design synthesis. Treating test and test logic early in the design reduces rework and allows performance and area tradeoffs to be investigated effectively.

Results produced by a prototype implementation indicate that test logic can be inserted into a network with very little performance or area overhead.

Index Terms:
test synthesis constraints, design for test, automatic rule violation repair
Henry Cox, "Synthesizing Circuits with Implicit Testability Constraints," IEEE Design & Test of Computers, vol. 12, no. 2, pp. 16-23, Summer 1995, doi:10.1109/54.386001
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