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Issue No.02 - Summer (1995 vol.12)
pp: 6-7
Published by the IEEE Computer Society
Butterflies undergo tremendous change, quietly assuming different forms. Testsynthesis behaves similarly, and has become many things to many people—whatthe end user really wants, what electronic design automation vendors currentlysupply, and what researchers see on the horizon. This issue of IEEE Design &Test reflects all these forms, drawing on the expertise demonstrated at the firstIEEE International Test Synthesis Workshop (Santa Barbara, May 1994) and theTest Synthesis Seminar held as part of the 25th IEEE International TestConference (Washington, D.C., October 1994).
Robert C. Aitken (Hewlett Packard) sets the scene with an end-user perspective oftest synthesis. He points out that "Everyone seems to know what test synthesis is,but few people agree on any given definition." Is it something that takes place atthe gate level? Or does it occur at a higher level, such as the register-transfer level?Aitken discusses both gate- and register-transfer level test synthesis and generallysurveys the approaches taken by EDA vendors, commenting on each method'scapabilities and limitations.
He sees gate-level tools as implementing a two-pass process. First, they synthesizefrom a hardware description language, such as VHDL or Verilog, down to the gatelevel. Then, they resynthesize to build scan-path structures and generate patterns.
RTL approaches lie more in the single-pass domain and synthesize testabilitystructures in the main design synthesis process. EDA vendors develop their currenttools from another synthesis tool's gate-level netlist, but a clear trend for the majorvendors is to upgrade their products to a single-pass system.
Aitken concludes with advice on choosing a test synthesis tool set. He points outthat first-time users should carefully think through their requirements from theperspectives of methodology and final test. What counts is not any single tool'sspeed, but the overall tool flow's ability to create a testable device complete with aworking test program. (In other words, go for the big picture before evaluatingdetailed features.)
Continuing with the pragmatic viewpoint, Henry Cox (Symplify Corporation) presentshow one EDA vendor carries out the front-end rule-checking phase of a two-pass testsynthesis tool set. Rule checking is critical to the downstream operations of scan-pathinsertion and pattern generation. For a given DFT methodology, such as full scan withmultiplexed D flip-flops, rule-checking identifies potential problems, such as buscontention during scan. It also assesses the controllability and observability of the stateflip-flops and carries out several checks based on the limitations of tools downstream.Cox presents detailed examples of rule violations and describes how to overcomethem.
The next two articles give us a glimpse of the test synthesis horizon. Kwang-Ting(Tim) Cheng (University of California, Santa Barbara) addresses pattern generation forpartial-scan sequential circuits, a practical problem at the back end of a test synthesisflow. A problem occurs in circuits based on multiplexed D flip-flops if we use thesystem clock as the scan clock during the scan operation: Nonscan flip-flops changetheir state during scan-in and scan-out. This state change invalidates the usualassumption of the reverse-time sequential pattern generation procedure—that is, thatany state can be scanned into the scan register without affecting the state of nonscanflip-flops. We can solve this state retention problem by
  • using the scan-enable control signal to gate the clock between the scan andnonscan elements such that, during scan mode, the nonscan elements are notclocked
  • converting the scan elements into clocked-scan flip-flops that use a separate scanclock for scan shifting and disabling the system clock during this operation
  • extending sequential pattern generation capability to accommodate the statechange of the nonscan elements
Method 1 carries a clock-skew penalty and method 2 requires greater silicon area.Cheng addresses method 3 and describes an extension to the Back algorithmaccounting for the behavior of all flip-flops during a single (reverse-time) clock pulse.Results based on the ISCAS89 benchmark circuits (from the 1989 InternationalSymposium on Circuits and Systems) indicate a potential loss of coverage (up to 4.2%)compared to gated-clock solutions. However, this method has the advantage of applyingtests in real time, thereby potentially detecting propagation-delay faults.
The last article is the collaborative effort of Carnegie Mellon and McGill Universities.Thomas Marchok et al. explore the implications of retiming on pattern-generationruntime and fault coverage. Retiming occurs in sequential circuit synthesis and involvesreplacing state flip-flops across sections of the combinational logic to improve acircuit's time-related behavior, usually at the expense of area. At the same time,retiming can increase the runtime of a sequential pattern generation tool and decreasefault coverage compared to the original circuit. This occurs because the retimed andoriginal circuits' state transition graphs differ, but their I/O behavior remains thesame. In particular, retiming can introduce equivalent (redundant) and invalid statesthat are unreachable from a reset state. Both affect the initialization of a circuit to aunique reset state via a synchronizing sequence and further complicate the patterngeneration procedure.
Experiment results indicate retiming's impact on runtime and fault coverage. In onecircuit, coverage dropped from 99.3% to 54.6% for a set of patterns that took 11.6times longer to generate. The authors explore possible causes of these results andfinally conclude that since retiming does not introduce logically redundant faults, thetest sets generated for the original circuit are also valid for the retimed circuits. Theycome to this conclusion by observing that retiming alters the clock cycle, but not thesequence, in which logic values move through a circuit; further experiments confirmthis. The authors' recommend a methodology in which we design the circuit andtests, implement retiming, and then confirm fault coverage with a fault simulator.
Conclusion
This issue attempts to portray the many faces of test synthesis, and overall theauthors present a balanced view. I believe test synthesis is about to undergo aformidable metamorphosis—from the current 2-pass, low-level approach to the higherlevel, more integrated 1-pass approach. As and when this happens, the synthesis ofhardware testability structures will become so fully integrated into the design processthat "design for test" will cease to be a visible and painful overhead. Instead, it willassume its rightful place as one of the many constraints at the start of the designprocess, challenging in its implementation, but rewarding in its value to the finalproduct.
My thanks go to the authors and referees for their efforts in bringing these articlesto publication.

R.G. (Ben) Bennetts is a senior test consultant with Synopsys, Inc. Prior to joiningSynopsys, Bennetts was a freelance consultant and lecturer on DFT topics withBennetts Associates, Southampton, UK. His consultancy has included technical andmarketing activities in test technology, test strategies, and DFT techniques, workingwith companies such as Philips and Alcatel. He has given tutorials at the IEEEInternational Test Conference and the European Test Conference. Bennetts was programchair for the first three ETCs and has published over 70 papers and two books on testsubjects. He was an invited speaker at ITC 92 and is currently general chair of theIEEE International Test Synthesis Workshop.


Address questions or comments about this special issue to Ben Bennetts at Synopsys(Northern Europe) Ltd., Imperium, Imperial Way, Worton Grange, Reading RG2 OTD,UK; benbsynopsys.com.
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