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System Partitioning of MCMs for Low Power
Spring 1995 (vol. 12 no. 1)
pp. 41-52
Low power design of large systems has traditionally relied on heuristics at the architectural, circuit and device levels to reduce the power dissipation. A systematic approach that efficiently partitions an MCM-based system for low power together with area, yield, reuse of cell libraries, and routing constraints has received little attention, largely because of its computational complexity and the lack of efficient optimization algorithms. This paper proposes a new four phase algorithm for system partitioning of MCMs under low power constraints, that is suitable for implementation with an integrated system prototyping environment. These algorithms utilize commercially available mixed integer programming software. This paper presents these models, explains our solutions via a simple example, and lists results of partitioning of large circuits for low power applications.
Index Terms:
Low-power electronics, system design, MCM-based systems, VLSI circuit design, multichip modules
Shoab A. Khan, Vijay K. Madisetti, "System Partitioning of MCMs for Low Power," IEEE Design & Test of Computers, vol. 12, no. 1, pp. 41-52, Spring 1995, doi:10.1109/54.350690
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