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Automatic Verification of Asynchronous Circuits
Spring 1995 (vol. 12 no. 1)
pp. 24-31
| ASCII Text | x | ||
| Trevor W.S. Lee, Mark R. Greenstreet, Carl-Johan Seger, "Automatic Verification of Asynchronous Circuits," IEEE Design & Test of Computers, vol. 12, no. 1, pp. 24-31, Spring, 1995. | |||
| BibTex | x | ||
| @article{ 10.1109/54.350687, author = {Trevor W.S. Lee and Mark R. Greenstreet and Carl-Johan Seger}, title = {Automatic Verification of Asynchronous Circuits}, journal ={IEEE Design & Test of Computers}, volume = {12}, number = {1}, issn = {0740-7475}, year = {1995}, pages = {24-31}, doi = {http://doi.ieeecomputersociety.org/10.1109/54.350687}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - Automatic Verification of Asynchronous Circuits IS - 1 SN - 0740-7475 SP24 EP31 EPD - 24-31 A1 - Trevor W.S. Lee, A1 - Mark R. Greenstreet, A1 - Carl-Johan Seger, PY - 1995 VL - 12 JA - IEEE Design & Test of Computers ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.350687
The verification of asynchronous designs is difficult, since design errors may only be manifested under rare circumstances. We show how asynchronous designs can be modeled as programs in the general-purpose hardware description language Synchronized Transitions, translated into the verification language, and how this representation facilitates rigorous and efficient verification of the designs.
Citation:
Trevor W.S. Lee, Mark R. Greenstreet, Carl-Johan Seger, "Automatic Verification of Asynchronous Circuits," IEEE Design & Test of Computers, vol. 12, no. 1, pp. 24-31, Spring 1995, doi:10.1109/54.350687
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