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Issue No.01 - Spring (1995 vol.12)
pp: 24-31
The verification of asynchronous designs is difficult, since design errors may only be manifested under rare circumstances. We show how asynchronous designs can be modeled as programs in the general-purpose hardware description language Synchronized Transitions, translated into the verification language, and how this representation facilitates rigorous and efficient verification of the designs.
Trevor W.S. Lee, Mark R. Greenstreet, Carl-Johan Seger, "Automatic Verification of Asynchronous Circuits", IEEE Design & Test of Computers, vol.12, no. 1, pp. 24-31, Spring 1995, doi:10.1109/54.350687
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