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Issue No.01 - Spring (1995 vol.12)
pp: 14-23
ABSTRACT
A procedure of designing a self-timed device defined by the model of finite automaton is suggested. In accordance with the chosen automaton standard implementation structure from the automaton transition/output graph one derives the Signal Graph Specification that then is processed by the formal synthesis procedure for self-timed implementation. The design procedure is illustrated by two examples: Stack Memory and Counter with Constant Acknowledge Delay.
CITATION
Victor I. Varshavsky, Vyacheslav B. Marakhovsky, Vadim V. Smolensky, "Designing Self-Timed Devices Using the Finite Automaton Model", IEEE Design & Test of Computers, vol.12, no. 1, pp. 14-23, Spring 1995, doi:10.1109/54.350685
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