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Saving Power by Synthesizing Gated Clocks for Sequential Circuits
October/December 1994 (vol. 11 no. 4)
pp. 32-41

Portable devices demand low power consumption to prolong battery life. Gating the clock is one strategy for saving power. The authors' technique identifies self-loops in an FSM and uses the function described by the self-loops to gate the clock. Applying these techniques to standard benchmarks achieved an average 25% less power dissipation at a cost of only 5% more area.

Citation:
Luca Benini, Polly Siegel, Giovanni De Micheli, "Saving Power by Synthesizing Gated Clocks for Sequential Circuits," IEEE Design & Test of Computers, vol. 11, no. 4, pp. 32-41, Oct.-Dec. 1994, doi:10.1109/54.329451
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