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TITAC: Design of A Quasi-Delay-Insensitive Microprocessor
April/June 1994 (vol. 11 no. 2)
pp. 50-63

TITAC is an asynchronous version of an 8-bit von Neumann microprocessor based on the delay-insensitive model incorporating the isochronic-forks assumption. In its two-phase, event-driven design scheme, a working phase and an idle phase alternate to execute control and data transfer. The data path design uses a two-rail, multilevel AND-OR scheme with a binary decision diagram structure for efficient signal generation.

Citation:
Takashi Nanya, Yoichiro Ueno, Hiroto Kagotani, Masashi Kuwako, Akihiro Takamura, "TITAC: Design of A Quasi-Delay-Insensitive Microprocessor," IEEE Design & Test of Computers, vol. 11, no. 2, pp. 50-63, April-June 1994, doi:10.1109/54.282445
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