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TITAC: Design of A Quasi-Delay-Insensitive Microprocessor
April/June 1994 (vol. 11 no. 2)
pp. 50-63
| ASCII Text | x | ||
| Takashi Nanya, Yoichiro Ueno, Hiroto Kagotani, Masashi Kuwako, Akihiro Takamura, "TITAC: Design of A Quasi-Delay-Insensitive Microprocessor," IEEE Design & Test of Computers, vol. 11, no. 2, pp. 50-63, April/June, 1994. | |||
| BibTex | x | ||
| @article{ 10.1109/54.282445, author = {Takashi Nanya and Yoichiro Ueno and Hiroto Kagotani and Masashi Kuwako and Akihiro Takamura}, title = {TITAC: Design of A Quasi-Delay-Insensitive Microprocessor}, journal ={IEEE Design & Test of Computers}, volume = {11}, number = {2}, issn = {0740-7475}, year = {1994}, pages = {50-63}, doi = {http://doi.ieeecomputersociety.org/10.1109/54.282445}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - TITAC: Design of A Quasi-Delay-Insensitive Microprocessor IS - 2 SN - 0740-7475 SP50 EP63 EPD - 50-63 A1 - Takashi Nanya, A1 - Yoichiro Ueno, A1 - Hiroto Kagotani, A1 - Masashi Kuwako, A1 - Akihiro Takamura, PY - 1994 VL - 11 JA - IEEE Design & Test of Computers ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.282445
TITAC is an asynchronous version of an 8-bit von Neumann microprocessor based on the delay-insensitive model incorporating the isochronic-forks assumption. In its two-phase, event-driven design scheme, a working phase and an idle phase alternate to execute control and data transfer. The data path design uses a two-rail, multilevel AND-OR scheme with a binary decision diagram structure for efficient signal generation.
Citation:
Takashi Nanya, Yoichiro Ueno, Hiroto Kagotani, Masashi Kuwako, Akihiro Takamura, "TITAC: Design of A Quasi-Delay-Insensitive Microprocessor," IEEE Design & Test of Computers, vol. 11, no. 2, pp. 50-63, April-June 1994, doi:10.1109/54.282445
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