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A Fault-Tolerant Digital Artificial Neuron
October/December 1993 (vol. 10 no. 4)
pp. 76-82
ASCII Text
x 
 
Fadi N. Sibai, "A Fault-Tolerant Digital Artificial Neuron," IEEE Design & Test of Computers, vol. 10, no. 4, pp. 76-82, October/December, 1993.
 
 
BibTex
x
 
@article{ 10.1109/54.245965,
author = {Fadi N. Sibai},
title = {A Fault-Tolerant Digital Artificial Neuron},
journal ={IEEE Design & Test of Computers},
volume = {10},
number = {4},
issn = {0740-7475},
year = {1993},
pages = {76-82},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.245965},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design & Test of Computers
TI - A Fault-Tolerant Digital Artificial Neuron
IS - 4
SN - 0740-7475
SP76
EP82
EPD - 76-82
A1 - Fadi N. Sibai,
PY - 1993
VL - 10
JA - IEEE Design & Test of Computers
ER -
 

A simple fault-tolerant digital artificial neuron is introduced. Two digital implementations based on two different adders are examined. Reliability, fault coverage, and hardware redundancy analyses are carried out to characterize the proposed fault-tolerant digital neural module. These analyses reveal that, for a 114% increase in hardware, a 92.07% fault detection coverage and a 21.15% fault recovery coverage are attained for a four-input neural module.

Citation:
Fadi N. Sibai, "A Fault-Tolerant Digital Artificial Neuron," IEEE Design & Test of Computers, vol. 10, no. 4, pp. 76-82, Oct.-Dec. 1993, doi:10.1109/54.245965
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