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Generating Tests for Delay Faults in Nonscan Circuits
January/March 1993 (vol. 10 no. 1)
pp. 20-28

A delay test method that allows any sequential-circuit test generation program to produce path delay tests for nonscan circuits is presented. Using this method, a given path is tested by augmenting the netlist model of the circuit with a logic block, in which testing for a certain single stuck-at fault is equivalent to testing for a path delay fault. The test sequence for the stuck-at fault performs all the necessary delay fault test functions: initialization, path activation, and fault propagation. Results on benchmarks are presented for nonscan and scan/hold modes of testing.

Citation:
Prathima Agrawal, Vishwani Agrawal, Sharad Seth, "Generating Tests for Delay Faults in Nonscan Circuits," IEEE Design & Test of Computers, vol. 10, no. 1, pp. 20-28, Jan.-March 1993, doi:10.1109/54.199801
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