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A New Testing Acceleration Chip for Low-Cost Memory Tests
January/March 1993 (vol. 10 no. 1)
pp. 15-19

It is argued that the development of semiconductor memories has reached a turning point. In the multimegabit dynamic random access memories (DRAMs) of the future, major factors contributing to the chip cost are process complexity, die size, equipment cost, and test cost. If conventional test methods are used, test costs will grow at an especially rapid rate. A memory test concept called the testing acceleration chip, which could reduce future test costs a hundredfold and yet maintain AC testing reliability, is presented.

Citation:
Michihiro Inoue, Toshio Yamada, Atsushi Fujiwara, "A New Testing Acceleration Chip for Low-Cost Memory Tests," IEEE Design & Test of Computers, vol. 10, no. 1, pp. 15-19, Jan.-March 1993, doi:10.1109/54.199800
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