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A Fast Partitioning Method for PLA-Based FPGAs
October/December 1992 (vol. 9 no. 4)
pp. 34-39

A method for automatic multipartitioning of a multiple-output logic function into the smallest number of subfunctions for mapping to fixed-size PLAs of a field-programmable gate array (FPGA) chip is described. A detailed example to demonstrate the procedure is presented. It is shown that, for this example, the method produced almost optimum partitions in a fast and efficient manner.

Citation:
Zafar Hasan, David Harrison, Maciej Ciesielski, "A Fast Partitioning Method for PLA-Based FPGAs," IEEE Design & Test of Computers, vol. 9, no. 4, pp. 34-39, Oct.-Dec. 1992, doi:10.1109/54.173331
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