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Empirical Failure Analysis and Validation of Fault Models in CMOS VLSI Circuits
January/March 1992 (vol. 9 no. 1)
pp. 72-83

A way to empirically validate fault models and to measure the effectiveness of test sets based on the targeted fault models is described. The authors use automated fault diagnosis of test circuits representative of the circuits being studied and of the fabrication process, cell libraries, and CAD tools used in their development. The design and fabrication of a test chip using an experimental CMOS, 1.5- mu m double-layer metal process are discussed.

Citation:
Ashish Pancholy, Janusz Rajski, Larry J. McNaughton, "Empirical Failure Analysis and Validation of Fault Models in CMOS VLSI Circuits," IEEE Design & Test of Computers, vol. 9, no. 1, pp. 72-83, Jan.-March 1992, doi:10.1109/54.124519
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