|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
 Digg  Furl  Spurl  Blink  Simpy  Google  Del.icio.us  Y!MyWeb | ||
| Search | ||
| ||
| ASCII Text | x | ||
| Mehrdad Bidjan-Irani, "A Rule-Based Design-for-Testability Rule Checker," IEEE Design & Test of Computers, vol. 8, no. 1, pp. 50-57, January/March, 1991. | |||
| BibTex | x | ||
| @article{ 10.1109/54.75663, author = {Mehrdad Bidjan-Irani}, title = {A Rule-Based Design-for-Testability Rule Checker}, journal ={IEEE Design & Test of Computers}, volume = {8}, number = {1}, issn = {0740-7475}, year = {1991}, pages = {50-57}, doi = {http://doi.ieeecomputersociety.org/10.1109/54.75663}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - A Rule-Based Design-for-Testability Rule Checker IS - 1 SN - 0740-7475 SP50 EP57 EPD - 50-57 A1 - Mehrdad Bidjan-Irani, PY - 1991 VL - 8 JA - IEEE Design & Test of Computers ER - | |||
An automatic design-for-testability (DFT) rule checker that can be used during early design stages at the register-transfer level is described. The system uses expert-system technology to check the correspondence of a rule set to a register-transfer level description of the design. In addition, it runs quickly and interactively, supports hierarchical design by checking subcircuits and groups of subcircuits, and provides concrete references about possible rule violations in the circuit and advice on how to eliminate them. The system accepts arbitrary DFT rule sets as input and analyzes highly integrated circuits hierarchically. Its output provides the location of rule violations or, if there are no violations, DFT descriptions of the circuit and the analysis protocol.