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Dynamic Functional Testing for VLSI Circuits
November/December 1990 (vol. 7 no. 6)
pp. 42-49
ASCII Text
x 
 
Peter M. Maurer, "Dynamic Functional Testing for VLSI Circuits," IEEE Design & Test of Computers, vol. 7, no. 6, pp. 42-49, November/December, 1990.
 
 
BibTex
x
 
@article{ 10.1109/54.64956,
author = {Peter M. Maurer},
title = {Dynamic Functional Testing for VLSI Circuits},
journal ={IEEE Design & Test of Computers},
volume = {7},
number = {6},
issn = {0740-7475},
year = {1990},
pages = {42-49},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.64956},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design & Test of Computers
TI - Dynamic Functional Testing for VLSI Circuits
IS - 6
SN - 0740-7475
SP42
EP49
EPD - 42-49
A1 - Peter M. Maurer,
PY - 1990
VL - 7
JA - IEEE Design & Test of Computers
ER -
 

The author discusses the two main problems of dynamic testing (i.e. testing while the simulator is running), namely the design of a high-level vector-generation language and the design of the interface between the vector generator and the simulator. He offers guidelines for designing a high-level vector-generation language as well as several examples written in FHDL, a driver language developed at the University of South Florida. The author also describes a solution to interface design that is based on a special interface data structure that supports several styles of vector generators and interactive circuit debugging.

Citation:
Peter M. Maurer, "Dynamic Functional Testing for VLSI Circuits," IEEE Design & Test of Computers, vol. 7, no. 6, pp. 42-49, Nov.-Dec. 1990, doi:10.1109/54.64956
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