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Issue No.04 - July/August (1990 vol.7)
pp: 26-31
ABSTRACT
<p>An implementation of a test-pattern generator based on the Podem (path-oriented decision-making) algorithm is proposed. Podem uses a depth-first search from the fault location to assign primary input values. The result of these assignments at internal nodes is then determined by logic simulation (implication). Podem must compute primary input combinations that both excite the fault and propagate it to primary outputs. The algorithm can be improved for high-activity circuits by packing more than one signal value into a word during implication. Packing introduces parallelism into the implication part of test generation and can be used to examine both the normal assignment and the alternative assignment to an input variable in parallel. With parallelism, the input space can be searched faster. To assess the benefits of such a scheme, compiled-code and event-driven version of the 'imply' function in Podem were implemented with and without the parallelism offered by value packing. Results show that conventional Podem with event-driven implication performs better for low-activity circuits, whereas Podem with compiled code and packed signal values performs better for high-activity circuits.</p>
CITATION
Kewal Saluja, Kyuchull Kim, "Improved Test Generation for High-Activity Circuits", IEEE Design & Test of Computers, vol.7, no. 4, pp. 26-31, July/August 1990, doi:10.1109/54.57910
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