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Verifying a Multiprocessor Cache Controller Using Random Test Generation
July/August 1990 (vol. 7 no. 4)
pp. 13-25

The design verification of the cache controller for SPUR, a shared-memory multiprocessor, is reported. The strategy was to develop a random tester that would generate and verify the complex interactions between multiple processors in functional simulation. Replacing the CPU model, the tester generates memory references by random selection from a script of actions and checks. It was easy to develop and detect over half the bugs uncovered during functional simulation. A prototype SPUR multiprocessor system that runs the Sprite operating system is being used for experiments in parallel programming. Results to data are described.

David A. Wood, Garth A. Gibson, Randy H. Katz, "Verifying a Multiprocessor Cache Controller Using Random Test Generation," IEEE Design & Test of Computers, vol. 7, no. 4, pp. 13-25, July-Aug. 1990, doi:10.1109/54.57906
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