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Issue No.03 - May/June (1990 vol.7)
pp: 25-32
ABSTRACT
<p>A package facility that enables designers to write models intuitively, without being forced to work with the underlying complexity and verboseness of the base VHDL (VHSIC hardware description language), is described. The VHDL environment handles all technology-dependent calculations automatically and drops in the lookup tables and utility function code as appropriate. In addition, the VHDL package facility automatically inserts the bus-resolution function where required, avoiding any need for the hardware designer to code or see this complex function. The package conforms strictly to the IEEE 1076-1987 specification and is therefore portable to a wide range of VHDL environments.</p>
CITATION
David R. Coelho, "A VHDL Standard Package for Logic Modeling", IEEE Design & Test of Computers, vol.7, no. 3, pp. 25-32, May/June 1990, doi:10.1109/54.56464
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