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Serial Interfacing for Embedded-Memory Testing
March/April 1990 (vol. 7 no. 2)
pp. 52-63

A serial interfacing scheme in which several embedded memories share the built-in, self-test circuit is presented. For external testing, this approach requires only two serial pins for access to the data path. There is considerable savings in routing area, and fewer external pins are needed to test random-access memories with wide words, such as those in application-specific integrated circuits for telecommunications. Even though the method uses serial access to the memory, a test pattern is applied every clock cycle because the memory itself shifts the test data. The method has been adapted to four common algorithms. In implementations of built-in self-test circuitry on several product chips, the area overhead was found to be acceptable.

Citation:
Benoit Nadeau-Dostie, Allan Silburt, Vinod K. Agarwal, "Serial Interfacing for Embedded-Memory Testing," IEEE Design & Test of Computers, vol. 7, no. 2, pp. 52-63, March-April 1990, doi:10.1109/54.53045
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