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Implementing Macro Test in Silicon Compiler Design
March/April 1990 (vol. 7 no. 2)
pp. 41-51

A testability strategy for a complex VLSI device that is implemented in the Piramid digital-signal-processor silicon compiler is presented. The macro test method proposed supports built-in self-test, scan test, restricted partial scan, and test-control logic at various levels in the design hierarchy. The strategy uses techniques such as a macro test plan, transfer information, and intermediate vector storage. The overhead from adding testability is only 10% of the total area and test-program generation is done with 100% fault coverage in a very short time, since there is no need for global test-pattern generation. A set of tools that guide the testability implementation from design to the final test program is described.

Frans Beenker, Barry J. Dekker, Richard Stans, Max Van der Star, "Implementing Macro Test in Silicon Compiler Design," IEEE Design & Test of Computers, vol. 7, no. 2, pp. 41-51, March-April 1990, doi:10.1109/54.53044
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