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Built-In Self-Test of the Macrolan Chip
March/April 1990 (vol. 7 no. 2)
pp. 29-40

The implementation of self-test in the medium access controller chip for Macrolan, a fibre-optic, local area network, is described. The test style for 80% of the chip's combinational logic is quasiexhaustive testing. This approach, despite its apparent inefficiency in terms of the number of patterns used, gives considerable flexibility to the designer in arranging linear-feedback shift registers and so is easier to implement than some other techniques. The chip also uses a form of random-pattern test, not normally considered for memory testing, instead of a specialized pattern generator. Built-in self-test was implemented without using fault simulation or approximate testability measures.

Citation:
Richard Illman, Stephen Clarke, "Built-In Self-Test of the Macrolan Chip," IEEE Design & Test of Computers, vol. 7, no. 2, pp. 29-40, March-April 1990, doi:10.1109/54.53043
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