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Low-Cost Testing of High-Density Logic Components
March/April 1990 (vol. 7 no. 2)
pp. 15-28

The evolution of a testing method and architecture of a logic-device tester to be used for the next generation of IBM's high-density CMOS ASIC (application-specific integrated circuit) logic components is described. The tester's design is based on the architecture of an existing IBM memory tester rather than on a conventional logic-tester design. The testing strategy calls for boundary-scan in each component design, built-in self-test logic within embedded memory arrays, and the use of weighted random-pattern logic testing. The development of the tester hardware is discussed, and capital costs of the new tester are compared with those of other approaches.

Robert W. Bassett, Barry J. Butkus, Stephen L. Dingle, Marc R. Faucher, Pamela S. Gillis, Jeannie H. Panner, John G. Petrovick Jr., Donald L. Wheater, "Low-Cost Testing of High-Density Logic Components," IEEE Design & Test of Computers, vol. 7, no. 2, pp. 15-28, March-April 1990, doi:10.1109/54.53042
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