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Issue No.05 - September/October (1989 vol.6)
pp: 58-77
ABSTRACT
<p>The authors present a technique, called test counting, for analyzing the testing requirements imposed on a combinational network in the form of a set of stuck-at faults to be detected. By solving a large set of mathematical inequalities, called constraints, test counting determines that certain pairs of faults cannot be test simultaneously. The result is a set of mutually independence faults, no two of which can be detected by the same test vector. The number of faults becomes a lower bound on the size of the test set required. The authors provide a list of constraints to implement the test-counting algorithm and offer a complete minimal test set for the 74LS181 ALU.</p>
CITATION
Sheldon B. Akers, Balakrishnan Krishnamurthy, "Test Counting: A Tool for VLSI Testing", IEEE Design & Test of Computers, vol.6, no. 5, pp. 58-77, September/October 1989, doi:10.1109/54.43080
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