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Parallel Simulated Annealing: Accuracy vs. Speed in Placement
May/June 1989 (vol. 6 no. 3)
pp. 8-34

The techniques that researchers have used to control error in VLSI placement are surveyed. The author discusses the application of parallelism, synchronization with serial subsets, combining algorithms, periodic synchronization, shared-memory implementation, local-memory implementation, and connection Machine implementation. The issues of temporary versus cumulative error, task allocation, and error measurements are examined.

Citation:
M.D. Durand, "Parallel Simulated Annealing: Accuracy vs. Speed in Placement," IEEE Design & Test of Computers, vol. 6, no. 3, pp. 8-34, May-June 1989, doi:10.1109/54.32410
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