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Parallel Simulated Annealing: Accuracy vs. Speed in Placement
May/June 1989 (vol. 6 no. 3)
pp. 8-34
ASCII Text
x 
 
M.D. Durand, "Parallel Simulated Annealing: Accuracy vs. Speed in Placement," IEEE Design & Test of Computers, vol. 6, no. 3, pp. 8-34, May/June, 1989.
 
 
BibTex
x
 
@article{ 10.1109/54.32410,
author = {M.D. Durand},
title = {Parallel Simulated Annealing: Accuracy vs. Speed in Placement},
journal ={IEEE Design & Test of Computers},
volume = {6},
number = {3},
issn = {0740-7475},
year = {1989},
pages = {8-34},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.32410},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design & Test of Computers
TI - Parallel Simulated Annealing: Accuracy vs. Speed in Placement
IS - 3
SN - 0740-7475
SP8
EP34
EPD - 8-34
A1 - M.D. Durand,
PY - 1989
VL - 6
JA - IEEE Design & Test of Computers
ER -
 

The techniques that researchers have used to control error in VLSI placement are surveyed. The author discusses the application of parallelism, synchronization with serial subsets, combining algorithms, periodic synchronization, shared-memory implementation, local-memory implementation, and connection Machine implementation. The issues of temporary versus cumulative error, task allocation, and error measurements are examined.

Citation:
M.D. Durand, "Parallel Simulated Annealing: Accuracy vs. Speed in Placement," IEEE Design & Test of Computers, vol. 6, no. 3, pp. 8-34, May-June 1989, doi:10.1109/54.32410
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