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| ASCII Text | x | ||
| Viktors Berstis, "The V Compiler: Automatic Hardware Design," IEEE Design & Test of Computers, vol. 6, no. 2, pp. 8-17, March/April, 1989. | |||
| BibTex | x | ||
| @article{ 10.1109/54.19131, author = {Viktors Berstis}, title = {The V Compiler: Automatic Hardware Design}, journal ={IEEE Design & Test of Computers}, volume = {6}, number = {2}, issn = {0740-7475}, year = {1989}, pages = {8-17}, doi = {http://doi.ieeecomputersociety.org/10.1109/54.19131}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - The V Compiler: Automatic Hardware Design IS - 2 SN - 0740-7475 SP8 EP17 EPD - 8-17 A1 - Viktors Berstis, PY - 1989 VL - 6 JA - IEEE Design & Test of Computers ER - | |||
The V language describes VLSI systems concisely through the use of sequential algorithmic descriptions. Because V includes high-level constructs such as queues, asynchronous calls, and cycle-blocks, designs are more readily described and optimized into efficient hardware implementations. The implementations can then be tuned for space, time, or other objectives using annotations. From the input description, the V compiler generates both a register-transfer-level specification and a software simulator. Thus, a single description is suitable for both functional simulation and input to logic synthesis. The author describes parsing. scheduling, and resource sharing using the V compiler. He discusses synthesis and simulation, annotations, and high-level constructs.

