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Issue No.02 - March/April (1989 vol.6)
pp: 35,36,37,38,39,40,41,42,43,44
ABSTRACT
The authors describe a high-level synthesis tool that addresses the broad range of throughput requirements inherent in all DSP (digital signal processor) systems. The primary role of this system, called FACE (flexible architecture compilation environment), is to provide a set of algorithms that adequately support architecturally specific hardware synthesis for a class of DSP applications. They first identify the shortcomings of Parsifal, an earlier synthesis system, and discuss the requirements for FACE. They examine briefly the architectural issues. They then describe FACE's synthesis algorithms.<>
INDEX TERMS
multiprocessing systems, circuit CAD, computer architecture, digital signal processing chips, synthesis algorithms, DSP systems, high-level synthesis tool, throughput requirements, digital signal processor, FACE, flexible architecture compilation environment, architecturally specific hardware synthesis, Parsifal, Digital signal processing, Algorithm design and analysis, Signal processing algorithms, Signal design, Hardware, Signal synthesis, Assembly, Throughput, Digital signal processing chips, Libraries
CITATION
"A synthesis environment for designing DSP systems", IEEE Design & Test of Computers, vol.6, no. 2, pp. 35,36,37,38,39,40,41,42,43,44, March/April 1989, doi:10.1109/54.19133
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