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Issue No.01 - January/February (1989 vol.6)
pp: 56-66
ABSTRACT
<p>The authors describe the successful postlayout verification of the WE DSP32 digital signal processor and the application of advanced CAD (computer-aided design) tools. The development work culminated in the smooth transfer of the DSP32 design into high-volume production. During this period, the authors were able to diagnose and repair hundreds of design errors. They also caught errors in the test-vector software and fixed them before first silicon. They estimate that their verification work saved the DSP32 project a year of silicon debugging. In addition, the authors were able to enhance the CAD tools themselves.</p>
CITATION
Chin-Fu Chen, Evelyn M. Fields, Renato N. Gadenz, W. Patrick Hays, Howard S. Moscovitz, Thomas G. Szymanski, "Post-Layout Verification of the WE DSP32 Digital Signal Processor", IEEE Design & Test of Computers, vol.6, no. 1, pp. 56-66, January/February 1989, doi:10.1109/54.20390
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