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Automated BIST for Sequential Logic Synthesis
November/December 1988 (vol. 5 no. 6)
pp. 22-32

An automated built-in self-test (BIST) technique for general sequential logic is described that can be used directly at all levels of testing from device testing through system diagnostics. The technique selectively replaces existing system memory elements with BIST flip-flop cells, which it then connects to form a circular chain. Data are compacted and test patterns are generated simultaneously. The approach has been incorporated in a system for behavioral model synthesis to implement BIST in VLSI devices based on standard cells and in circuit packs based on PLDs, automatically. Seven production VLSI devices have been implemented with this automated BIST approach. Area overhead was between 6% and 19% for a fault coverage of 90%+ with the BIST capability alone.

Citation:
Charles E. Stroud, "Automated BIST for Sequential Logic Synthesis," IEEE Design & Test of Computers, vol. 5, no. 6, pp. 22-32, Nov.-Dec. 1988, doi:10.1109/54.9269
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