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Issue No.04 - July/August (1988 vol.5)
pp: 29-36
<p>A built-in test structure is described that is based on the ATS algorithmic test sequence, which provides the shortest possible test for stuck-at faults in a random-access memory (RAM). An initialization step has been added to ATS that allows the modified procedure to detect bit-rail faults. In the test mode, the memory address register is converted to a count-by-three circuit controlled by a four-latch test sequencer. A simple data-compare circuit is placed on the RAM outputs to detect faults.</p>
Paul H. Bardell Jr., William H. McAnney, "Built-In Test for RAMs", IEEE Design & Test of Computers, vol.5, no. 4, pp. 29-36, July/August 1988, doi:10.1109/54.7967
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