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Chip-Level Modeling with HDLs
January/February 1988 (vol. 5 no. 1)
pp. 8-18

VLSI circuits have made gate-level modeling of large-scale systems impractical. Chip-level modeling offers an alternative approach to model development that still represents timing accurately. The authors examine this approach to modeling and the use of hardware description languages (HDLs) to achieve the desired accuracy. The characteristics of chip-level models are reviewed and sample models are presented. HDL code for each model is given to illustrate its use. Fault modeling in a chip level is examined.

Citation:
J.R. Armstrong, "Chip-Level Modeling with HDLs," IEEE Design & Test of Computers, vol. 5, no. 1, pp. 8-18, Jan.-Feb. 1988, doi:10.1109/54.667
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