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Chip-Level Modeling with HDLs
January/February 1988 (vol. 5 no. 1)
pp. 8-18
| ASCII Text | x | ||
| J.R. Armstrong, "Chip-Level Modeling with HDLs," IEEE Design & Test of Computers, vol. 5, no. 1, pp. 8-18, January/February, 1988. | |||
| BibTex | x | ||
| @article{ 10.1109/54.667, author = {J.R. Armstrong}, title = {Chip-Level Modeling with HDLs}, journal ={IEEE Design & Test of Computers}, volume = {5}, number = {1}, issn = {0740-7475}, year = {1988}, pages = {8-18}, doi = {http://doi.ieeecomputersociety.org/10.1109/54.667}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - Chip-Level Modeling with HDLs IS - 1 SN - 0740-7475 SP8 EP18 EPD - 8-18 A1 - J.R. Armstrong, PY - 1988 VL - 5 JA - IEEE Design & Test of Computers ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.667
VLSI circuits have made gate-level modeling of large-scale systems impractical. Chip-level modeling offers an alternative approach to model development that still represents timing accurately. The authors examine this approach to modeling and the use of hardware description languages (HDLs) to achieve the desired accuracy. The characteristics of chip-level models are reviewed and sample models are presented. HDL code for each model is given to illustrate its use. Fault modeling in a chip level is examined.
Citation:
J.R. Armstrong, "Chip-Level Modeling with HDLs," IEEE Design & Test of Computers, vol. 5, no. 1, pp. 8-18, Jan.-Feb. 1988, doi:10.1109/54.667
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