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Issue No.05 - September/October (1987 vol.4)
pp: 28-36
P. Agrawal , AT&T Bell Laboratories
W.J. Dally , AT&T Bell Laboratories
W.C. Fischer , AT&T Bell Laboratories
H.V. Jagadish , AT&T Bell Laboratories
A.S. Krishnakumar , AT&T Bell Laboratories
R. Tutundjian , AT&T Bell Laboratories
ABSTRACT
MARS, short for microprogrammable accelerator for rapid simulations, is a multiprocessor-based hardware accelerator that canefficiently implement a wide range of computationally complex algorithms. In addition to accelerating many graph-related problemsolutions, MARS is ideally suited for performing event-driven simulations of VLSI circuits. Its highly pipelined and parallelarchitecture yields a performance comparable to that of existing special-purpose hardware simulators. MARS has the added advantageof flexibility because its VLSI processors are custom-designed to be microprogrammable and reconfigurable. When programmedas a logic simulator, MARS should be able to achieve 1 million gate evaluations per second.
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CITATION
P. Agrawal, W.J. Dally, W.C. Fischer, H.V. Jagadish, A.S. Krishnakumar, R. Tutundjian, "MARS: A Multiprocessor-Based Programmable Accelerator", IEEE Design & Test of Computers, vol.4, no. 5, pp. 28-36, September/October 1987, doi:10.1109/MDT.1987.295211
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