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Issue No.04 - July/August (1987 vol.4)
pp: 18-25
John Hayes , University of Michigan
ABSTRACT
Switch-level modeling is a recently developed design and analysis methodology for MOS VLSI circuits. At the switch level,important features of MOS circuits can be directly modeled using a moderate number of discrete parameters, including switchstates, resistance, capacitance, and bidirectional signals. Switch-level models, provide more accurate behavioral and structuralinformation than gate-level logical models, while avoiding the high computational cost associated with analog electrical models.
INDEX TERMS
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CITATION
John Hayes, "An Introduction to Switch-Level Modeling", IEEE Design & Test of Computers, vol.4, no. 4, pp. 18-25, July/August 1987, doi:10.1109/MDT.1987.295145
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