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Issue No.02 - March/April (1987 vol.4)
pp: 32-38
ABSTRACT
Delay fault testing is becoming more important as VLSI chips become more complex. Components that are fragments of functions,such as those in gate-array designs, need a general model of a delay fault and a feasible method of generating test patternsand simulating the fault. The authors present such a model, called a transition fault, which when used with parallel-pattern,single-fault propagation, is an efficient way to simulate delay faults. The authors describe results from 10 benchmark designsand discuss add-ons to a stuck fault simulator to enable transition fault simulation. Their experiments show that delay faultsimulation can be done of random patterns in less than 10% more time than needed for a stuck fault simulation.
INDEX TERMS
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CITATION
John Waicukauski, Eric Lindbloom, Barry Rosen, Vijay Iyengar, "Transition Fault Simulation", IEEE Design & Test of Computers, vol.4, no. 2, pp. 32-38, March/April 1987, doi:10.1109/MDT.1987.295104
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