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Issue No.02 - March/April (1987 vol.4)
pp: 22-30
Mark Barber , AT&T Bell Laboratories
Walter Satre , AT&T Bell Laboratories
ABSTRACT
LSI test systems built in the 1970s had compact, 60-pin test heads that presented devices under test with open wires leadingto lumped-capacitive loads. Today's VLSI testers have 256-pin test heads with transmission lines leading from the DUTs todriver-comparator circuits that are as far away as 50 cm. Even though these automatic testers are adjusted to subnanosecondaccuracy, reflections within the transmission lines can cause timing measurement errors up to 10 ns for MOS devices whoseoutput impedances are not matched to the transmission lines. The authors offer the Advice circuit simulator (an AT&T proprietaryversion of SPICE) as one way to analyze errors due to transmission line problems before testing. They also discuss ways tocorrect timing errors. Finally, they recommend that very high speed ICs be designed to drive transmission lines that are terminatedwith matched resistors at the comparators.
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CITATION
Mark Barber, Walter Satre, "Timing Accuracy in Modern ATE", IEEE Design & Test of Computers, vol.4, no. 2, pp. 22-30, March/April 1987, doi:10.1109/MDT.1987.295102
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