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| ASCII Text | x | ||
| Sudhakar Reddy, R. Dandapani, "Scan Design Using Standard Flip-Flops," IEEE Design & Test of Computers, vol. 4, no. 1, pp. 52-54, January/February, 1987. | |||
| BibTex | x | ||
| @article{ 10.1109/MDT.1987.295115, author = {Sudhakar Reddy and R. Dandapani}, title = {Scan Design Using Standard Flip-Flops}, journal ={IEEE Design & Test of Computers}, volume = {4}, number = {1}, issn = {0740-7475}, year = {1987}, pages = {52-54}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.1987.295115}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - Scan Design Using Standard Flip-Flops IS - 1 SN - 0740-7475 SP52 EP54 EPD - 52-54 A1 - Sudhakar Reddy, A1 - R. Dandapani, PY - 1987 KW - null VL - 4 JA - IEEE Design & Test of Computers ER - | |||
Classical scan designs require properly augmented flip-flops, often called scan flip-flops. Problems stem from the high areaoverhead implied by the need for these flip-flops or the inability to modify standard flip-flops. The authors outline a methodto design easily testable sequential circuits that achieve scan designs using standard (unmodified) flip-flops.
Citation:
Sudhakar Reddy, R. Dandapani, "Scan Design Using Standard Flip-Flops," IEEE Design & Test of Computers, vol. 4, no. 1, pp. 52-54, Jan.-Feb. 1987, doi:10.1109/MDT.1987.295115
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