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Issue No.06 - November/December (1986 vol.3)
pp: 13-25
H. Man , IMEC
J. Rabaey , IMEC
P. Six , IMEC
L. Claesen , IMEC
ABSTRACT
The article describes the status of work at IMEC on the Cathedral-II silicon compiler. The compiler was developed to synthesizesynchronous multiprocessor system chips for digital signal processing. It is a continuation of work on the Cathedral-I operationalsilicon compiler for bit-serial digital filters. Cathedral-II is based on a ?meet in the middle? design method that encouragesa total separation between system design and reusable silicon design. The CAD system includes a rule-based synthesis program,a procedural program, and a controller synthesis environment. Processors are synthesized in terms of modules called from automatedreusable module generators. Chip layout is done on a floor planner. An expert subsystem verifies correctness during silicondesign and generates functional and timing models for verification at the module and chip levels.
INDEX TERMS
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CITATION
H. Man, J. Rabaey, P. Six, L. Claesen, "Cathedral-II: A Silicon Compiler for Digital Signal Processing", IEEE Design & Test of Computers, vol.3, no. 6, pp. 13-25, November/December 1986, doi:10.1109/MDT.1986.295047
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