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Issue No.05 - September/October (1986 vol.3)
pp: 27-37
Sunil Jain , AT&T Bell Laboratories
Charles Stroud , AT&T Bell Laboratories
The authors present a built-in self-test (BIST) method for testing embedded memories. Two algorithms are proposed for self-testingof embedded bedded RAMs, both of which can detect a large variety of stuck-at and non-stuck-at faults. The hardware implementationof the methods requires a hardware test-pattern generator, which produces address, data, and read/write inputs. The outputresponses of the memory can be compressed by using a parallel input signature analyzer, or they can be compared with expectedresponses by an output comparator. The layout of memories has been considered in the design of additional BIST circuitry.The authors conclude by evaluating the two schemes on the basis of area overhead, performance degradation, fault coverage,test application time, and testing of self-test circuitry. The BIST overhead is very low and test time is quite short. Sixdevices, with one of the test schemes, have been manufactured and are in the field.
Sunil Jain, Charles Stroud, "Built-in Self Testing of Embedded Memories", IEEE Design & Test of Computers, vol.3, no. 5, pp. 27-37, September/October 1986, doi:10.1109/MDT.1986.295041
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