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SMART And FAST: Test Generation for VLSI Scan-Design Circuits
July/August 1986 (vol. 3 no. 4)
pp. 43-54
M. Abramovici, AT&T Information Systems
J.J. Kulikowski, AT&T Information Systems
P.R. Menon, AT&T Information Systems
D.T. Miller, AT&T Information Systems
This article describes new concepts and algorithms used to generate tests for VLSI scan-design circuits. The new algorithmsinclude: 1. a low-cost fault-independent algorithm (SMART), 2. a fault-oriented algorithm (FAST), and 3. an algorithm fordynamic test set compaction. The fault-oriented algorithm is guided by new controllability/observability cost functions whoseobjective is to minimize the amount of search done in test generation.
Citation:
M. Abramovici, J.J. Kulikowski, P.R. Menon, D.T. Miller, "SMART And FAST: Test Generation for VLSI Scan-Design Circuits," IEEE Design & Test of Computers, vol. 3, no. 4, pp. 43-54, July-Aug. 1986, doi:10.1109/MDT.1986.294975
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