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Integrating an Electron-Beam System into VLSI Fault Diagnosis
July/August 1986 (vol. 3 no. 4)
pp. 23-29
| ASCII Text | x | ||
| Teruo Tamama, Norio Kuji, "Integrating an Electron-Beam System into VLSI Fault Diagnosis," IEEE Design & Test of Computers, vol. 3, no. 4, pp. 23-29, July/August, 1986. | |||
| BibTex | x | ||
| @article{ 10.1109/MDT.1986.294966, author = {Teruo Tamama and Norio Kuji}, title = {Integrating an Electron-Beam System into VLSI Fault Diagnosis}, journal ={IEEE Design & Test of Computers}, volume = {3}, number = {4}, issn = {0740-7475}, year = {1986}, pages = {23-29}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.1986.294966}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - Integrating an Electron-Beam System into VLSI Fault Diagnosis IS - 4 SN - 0740-7475 SP23 EP29 EPD - 23-29 A1 - Teruo Tamama, A1 - Norio Kuji, PY - 1986 KW - null VL - 3 JA - IEEE Design & Test of Computers ER - | |||
Using design data, the system can prepare a logic-state map for the device under test. The map draws top-layer connectionsin different colors according to their expected logic states so the map may be compared to the DUT image observed by the electron-beamtester. The system has successfully tested a 75K-transistor VLSI device.
Citation:
Teruo Tamama, Norio Kuji, "Integrating an Electron-Beam System into VLSI Fault Diagnosis," IEEE Design & Test of Computers, vol. 3, no. 4, pp. 23-29, July-Aug. 1986, doi:10.1109/MDT.1986.294966
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