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Issue No.04 - July/August (1986 vol.3)
pp: 23-29
Teruo Tamama , NTT Electrical Communications Laboratories
Norio Kuji , NTT Electrical Communications Laboratories
ABSTRACT
Using design data, the system can prepare a logic-state map for the device under test. The map draws top-layer connectionsin different colors according to their expected logic states so the map may be compared to the DUT image observed by the electron-beamtester. The system has successfully tested a 75K-transistor VLSI device.
INDEX TERMS
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CITATION
Teruo Tamama, Norio Kuji, "Integrating an Electron-Beam System into VLSI Fault Diagnosis", IEEE Design & Test of Computers, vol.3, no. 4, pp. 23-29, July/August 1986, doi:10.1109/MDT.1986.294966
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