Issue No.03 - May/June (1986 vol.3)
K.L. Kodandapani , Digital Equipment Corporation
We will describe a wirelist compare program that, together with a VLSI node extractor, is used to verify VLSI IC layout connectivity.Engineers at Digital Equipment Corporation have successfully used this tool in a production environment to debug layout errors.The program is based on a graph isomorphism algorithm and provides graphical and textual guides to pinpoint errors. We willexamine this algorithm, its error outputs, and provide run-time statistics.
K.L. Kodandapani, "A Wirelist Compare Program for Verifying VLSI Layouts", IEEE Design & Test of Computers, vol.3, no. 3, pp. 46-51, May/June 1986, doi:10.1109/MDT.1986.294992