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Issue No.01 - January/February (1986 vol.3)
pp: 66-74
Louis Scheffer , Valid Logic Systems, Inc.
Ronny Soetarman , Valid Logic Systems, Inc.
ABSTRACT
Hierarchical design rule check and component extract offer many advantages, but no single form of hierarchical analysus fitsal situations. However, we will deal with hierarchical analyses which allow the user to specify how abstract representationsof cells are formed, how they are checked, and how to respond if a violation is detected. This allows one analysis fits allsituations. However, we will deal with hierarchical analyses which allow the user to specify how abstract representationsof cells are formed, how they are checked, and how to respond if a violation is detected. This allows one analysis program(with different rules) to use the designer's hierarchy for a wide variety of analyses. Analyses that were difficult in previousschemes (cross-coupling capacitances, terminals in the center of cells, and multilayer interconnects) can now be handled hierarchically.An analysis of existing custom VLSI chips reveals how designers use hierarchy. While they commonly add geometry across hierarchicalboundaries, designers rarely change the circuits of subcells?implying that hierarchical analysis is practical for a wide varieryof analysis is practical for a wide variety of analyses. Cases where hiearchical analysis is not practical, limited in variety,can be handled automatically by using differemt rules depending on the cell type.
INDEX TERMS
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CITATION
Louis Scheffer, Ronny Soetarman, "Hierarchical Analysis of IC Artwork with User-Defined Rules", IEEE Design & Test of Computers, vol.3, no. 1, pp. 66-74, January/February 1986, doi:10.1109/MDT.1986.294941
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