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Magic's Circuit Extractor
January/February 1986 (vol. 3 no. 1)
pp. 24-34
Walter Scott, University of California, Berkeley
John Ousterhout, University of California, Berkeley
This fast hierarchical circuit extractor for the Magic VLSI layout system derives its speed from its ability to handle hiearchicalarrays, and from a new algorithm based on corner-stitching, a geometrical data structure for representing Manhattan shapes.Corner-stitching's ability to find adjacent mask information is critical to the basic extractor speed, and its ability tosearch areas makes the hiearchical extraction algorithm practical. The extractor is incremental, necessitating re-extractionof only a few cells after a layout is modified. It accepts a hierarchical layout that may contain nearly arbitrary overlapsbetween cells, and produces a circuit description with the same hierarchical structure as the layout. The extractor can completelyextract a 37,000-transistor chip in 20 minutes of VAX CPU time, or incremetally in an average of 8 minutes. The extractorprocesses 50-65 FETS per second on a VAX-11/780 running Unix. if only substrate capacitance is being extracted. If couplingcapacitance is also extracted, the basic extractor processes 25-35 transistors per second.
Citation:
Walter Scott, John Ousterhout, "Magic's Circuit Extractor," IEEE Design & Test of Computers, vol. 3, no. 1, pp. 24-34, Jan.-Feb. 1986, doi:10.1109/MDT.1986.294914
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