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An Automatic Test-Generation System for Large Digital Circuits
September/October 1985 (vol. 2 no. 5)
pp. 54-60
Shigehiro Funatsu, NEC Corporation
Masato Kawai, NEC Corporation
A new test-generation system (FUTURE) for large digital circuits (more than 10K gates) is based on a nine-valued FAN algorithm.Fault simulation adopts a concurrent simulation adopts a concurrent simulation technique. The system consists of four majormodules: fault modeling, random pattern generation, algorithmic pattern generation, and fault simulation. The system can bea powerful CAD tool and effectively generate test patterns for large sequential circuits with Scan Path.
Citation:
Shigehiro Funatsu, Masato Kawai, "An Automatic Test-Generation System for Large Digital Circuits," IEEE Design & Test of Computers, vol. 2, no. 5, pp. 54-60, Sept.-Oct. 1985, doi:10.1109/MDT.1985.294817
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