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LORES-2: A Logic Reorganization System
September/October 1985 (vol. 2 no. 5)
pp. 35-42
| ASCII Text | x | ||
| Kiyoshi Enomoto, Shunichiro Nakamura, Takuji Ogihara, Shinichi Murai, "LORES-2: A Logic Reorganization System," IEEE Design & Test of Computers, vol. 2, no. 5, pp. 35-42, September/October, 1985. | |||
| BibTex | x | ||
| @article{ 10.1109/MDT.1985.294814, author = {Kiyoshi Enomoto and Shunichiro Nakamura and Takuji Ogihara and Shinichi Murai}, title = {LORES-2: A Logic Reorganization System}, journal ={IEEE Design & Test of Computers}, volume = {2}, number = {5}, issn = {0740-7475}, year = {1985}, pages = {35-42}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.1985.294814}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - LORES-2: A Logic Reorganization System IS - 5 SN - 0740-7475 SP35 EP42 EPD - 35-42 A1 - Kiyoshi Enomoto, A1 - Shunichiro Nakamura, A1 - Takuji Ogihara, A1 - Shinichi Murai, PY - 1985 KW - null VL - 2 JA - IEEE Design & Test of Computers ER - | |||
LORES-2 is a logic reorganization system which greatly contributes to the effective automation of logic design. LORES-2 usesa macro-expansion technique to help designers transform printed-circuit assembly logic composed of SSI and MSI circuits intomaster-slice LSI logic circuits. The number of gates of the most reorganized LSI circuit falls within ? 20 percent of thenumber of gates of the original circuit. When ROMS and/or PLAs are not-allowed on the target LSI circuit, those elements areconverted into optimized, multilevel random logic using logic minimization, factoring and macro-expansion techniques.
Citation:
Kiyoshi Enomoto, Shunichiro Nakamura, Takuji Ogihara, Shinichi Murai, "LORES-2: A Logic Reorganization System," IEEE Design & Test of Computers, vol. 2, no. 5, pp. 35-42, Sept.-Oct. 1985, doi:10.1109/MDT.1985.294814
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