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LORES-2: A Logic Reorganization System
September/October 1985 (vol. 2 no. 5)
pp. 35-42
Kiyoshi Enomoto, Mitsubishi Electric Corporation
Shunichiro Nakamura, Mitsubishi Electric Corporation
Takuji Ogihara, Mitsubishi Electric Corporation
Shinichi Murai, Mitsubishi Electric Corporation
LORES-2 is a logic reorganization system which greatly contributes to the effective automation of logic design. LORES-2 usesa macro-expansion technique to help designers transform printed-circuit assembly logic composed of SSI and MSI circuits intomaster-slice LSI logic circuits. The number of gates of the most reorganized LSI circuit falls within ? 20 percent of thenumber of gates of the original circuit. When ROMS and/or PLAs are not-allowed on the target LSI circuit, those elements areconverted into optimized, multilevel random logic using logic minimization, factoring and macro-expansion techniques.
Citation:
Kiyoshi Enomoto, Shunichiro Nakamura, Takuji Ogihara, Shinichi Murai, "LORES-2: A Logic Reorganization System," IEEE Design & Test of Computers, vol. 2, no. 5, pp. 35-42, Sept.-Oct. 1985, doi:10.1109/MDT.1985.294814
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