This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
An Integrated Design Automation System for VLSI Circuits
September/October 1985 (vol. 2 no. 5)
pp. 17-26
ASCII Text
x 
 
O. Karatsu, T. Hoshino, M. Endo, H. Kitazawa, T. Adachi, K. Ueda, "An Integrated Design Automation System for VLSI Circuits," IEEE Design & Test of Computers, vol. 2, no. 5, pp. 17-26, September/October, 1985.
 
 
BibTex
x
 
@article{ 10.1109/MDT.1985.294812,
author = {O. Karatsu and T. Hoshino and M. Endo and H. Kitazawa and T. Adachi and K. Ueda},
title = {An Integrated Design Automation System for VLSI Circuits},
journal ={IEEE Design & Test of Computers},
volume = {2},
number = {5},
issn = {0740-7475},
year = {1985},
pages = {17-26},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.1985.294812},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design & Test of Computers
TI - An Integrated Design Automation System for VLSI Circuits
IS - 5
SN - 0740-7475
SP17
EP26
EPD - 17-26
A1 - O. Karatsu,
A1 - T. Hoshino,
A1 - M. Endo,
A1 - H. Kitazawa,
A1 - T. Adachi,
A1 - K. Ueda,
PY - 1985
KW - null
VL - 2
JA - IEEE Design & Test of Computers
ER -
 
O. Karatsu, Atsugi Electrical Communication Laboratories
T. Hoshino, Atsugi Electrical Communication Laboratories
M. Endo, Atsugi Electrical Communication Laboratories
H. Kitazawa, Atsugi Electrical Communication Laboratories
T. Adachi, Atsugi Electrical Communication Laboratories
K. Ueda, Atsugi Electrical Communication Laboratories
Our Integrated Design Automation System consists of an integrated design database, automated design processors, verificationtools, and an interactive capture system. The automatic logic synthesis program, Angel, and the hierarchical layout systemChamp/Alpha, have been particularly important in reducing the total design effort. A unified design language, HSL-FX, hasbeen developed to broaden LSI design system coverage and to obtain better results from automatic logic synthesis. Using thissystem, a 10K-gate CPU has been designed in two man-months?from function-level description to layour pattern.
Citation:
O. Karatsu, T. Hoshino, M. Endo, H. Kitazawa, T. Adachi, K. Ueda, "An Integrated Design Automation System for VLSI Circuits," IEEE Design & Test of Computers, vol. 2, no. 5, pp. 17-26, Sept.-Oct. 1985, doi:10.1109/MDT.1985.294812
Usage of this product signifies your acceptance of the Terms of Use.