This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
A Knowledge-Based System for Designing Testable VLSI Chips
July/August 1985 (vol. 2 no. 4)
pp. 56-68
Magdy Abadir, University of Southern California
Melvin Breuer, University of Southern California
The complexity of VLSI circuits has increased the need for design for testability (DFT). Numerous techniques for designingmore easily tested circuits have evolved over the years, with particular emphasis on built-in testing approaches. What hasnot evolved is a design methodology for evaluating and making choices among the numerous existing approaches. This articledescribes efforts to build a knowledge-based expert system for designing testable VLSI chips. A framework for a methodologyincorporating structural, behavioral, qualitative, and quantitative aspects of known DFT techniques is introduced. This methodologyprovides a designer with a systematic DFT synthesis approach. The process of partitioning a design into subcircuits for individualprocessing is described and a new concept?I-path?is used to transfer data from one place in the circult to another. Rulesfor applying testable design methodologies to circuit partitions and for evaluating the various solutions obtained are alsopresented. Finally, a case study using a prototype system is described.
Citation:
Magdy Abadir, Melvin Breuer, "A Knowledge-Based System for Designing Testable VLSI Chips," IEEE Design & Test of Computers, vol. 2, no. 4, pp. 56-68, July-Aug. 1985, doi:10.1109/MDT.1985.294746
Usage of this product signifies your acceptance of the Terms of Use.