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Issue No.02 - March/April (1985 vol.2)
pp: 37-48
Robert Treuer , McGill University
Hideo Fujiwara , McGill University
Vinod Agarwal , McGill University
ABSTRACT
An NMOS implementation of a new built-in self-test PLA design is presented. The layouts for its additional test circuitryresult in appoximately 15-percent overhead for most large PlAS, a significantly better overhead than that of any existingscheme. Both the input test patterns and the output responses, which are compressed intoastring of parity bits, are independentof the functions that the PLA realizes, and the 15-percent overhead includes the storage needed for the fault-free compressedoutput data. The fault coverage of this approach consists of all single and (1-2 -( 2n + m)) of all multiple stuck, crosspoint,and bridging faults in the original PLA and the additional test circuitry (n and m are the number of input variables and productterms, respectively). The article begins with a short review of existing design schemes.
INDEX TERMS
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CITATION
Robert Treuer, Hideo Fujiwara, Vinod Agarwal, "Implementing a Built-In Self-Test PLA Design", IEEE Design & Test of Computers, vol.2, no. 2, pp. 37-48, March/April 1985, doi:10.1109/MDT.1985.294859
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