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Hierarchical Layout Verification
January/February 1985 (vol. 2 no. 1)
pp. 31-37
Todd Wagner, Intel
This article presents a hierarchical cell structure that has been Used successfully to improve the performance of Intel'sconnectivity verifier and design rule checker. A unique algorithm for performing design rule checks efficiently in a hierarchicalenvironment is discussed in detail. To undersize and oversize in a hierarchical environment without disrupting the cell structure,the definition of sizing must be changed so that geometries inside a cell and touching the cell boundaries do not pull awayand geometries outside the cell do not extend inside. There are also a few Pathologies?caused mostly by looking at only asmall portion of the layout, outside of the context where it is used. Nevertheless, careful use of hierarchical design candeliver order-of-magnitude improvements in layout checking runtime.
Todd Wagner, "Hierarchical Layout Verification," IEEE Design & Test of Computers, vol. 2, no. 1, pp. 31-37, Jan.-Feb. 1985, doi:10.1109/MDT.1985.294682
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