Moore's law, the famous axiom by which the computer industry has measured performance and price for 40 years, has been considered to be in long-term danger for quite some time. At some point, experts say, creating a new generation of transistors that double performance in the same amount of space will become physically impossible. That day has yet to arrive, however, and a spate of recent announcements and research papers suggests that it might continue receding into some farther future.

Recent announcements from two major chip manufacturers, Intel and IBM, underscore the nebulous situation surrounding the "someday" warnings and the continual march of competing R&D efforts.

On 27 January, Intel announced it had achieved product-quality chips composed of 45-nanometer transistors. The new chips use hafnium oxide instead of the industry-standard silicon dioxide on the gate dielectric of each transistor. Intel's press materials called the announcement the "biggest change to computer chips in 40 years" and "one of the biggest advancements in fundamental transistor design." But just two days after Intel's announcement, IBM also said it was perfecting its 45-nanometer technology and expected to have it in production by 2008.

A senior researcher at Hewlett-Packard says the announcements didn't startle industry insiders a bit, and the two biggest players making tit-for-tat claims might bear that out.

"This has been part of the ITRS [International Technology Roadmap for Semiconductors] for a long time," says Stan Williams, a senior research fellow at HP Labs. "The whole issue of hafnium oxide is just keeping Moore's law rolling. It was the next necessary step. In a sense, it's a significant issue for Intel and IBM because it does mean a big difference in their manufacturing, but for those in the community, this was not a big surprise."

However, Williams and his colleagues and competitors at research labs worldwide are working on technologies that could indeed surprise the industry. These "next generation plus" semiconductor technologies exploit nanotechnologies. In some cases, they exploit materials other than metals, and they often use other scientific disciplines' principles to advance the physics of electronic calculation. Taken together, the industry's major players have recently announced discoveries at a rate that might provide a composite view of likely standards for logic processing, interconnect technology, and heat control.

Nanotechnology is the key element of next-generation chip research. For HP Labs, the highlight is a nanowire interconnect technology. Researchers elsewhere are examining the use of carbon nanotubes and silicon nanophotonics through optical fiber. Yet, despite the emphasis on materials other than silicon, Williams says Moore's law—originally defined by Intel cofounder Gordon Moore in 1965, just at the dawn of the integrated-circuit age—will remain the industry's shibboleth for quite some time.

"All along our plan has been to try not to overthrow Moore's law," he says. "We're not that crazy. We know what we have to do is effectively come in and hybridize with it or steer it in other directions."

Yet, Williams also contends that the principle of Moore's law is actually a moving target.

"Moore's law has been amended many times," he says. "It started off as the doubling of the number of transistors on a chip, but has most recently been the doubling of capacity at constant cost. That's kind of in trouble right now with all these issues of having to go over to multicore processors and all that stuff."

The essence of the expected trouble for Moore's law is a combination of existing technology's physical limits and the semiconductor industry's understandable preference to leverage their investments in the manufacturing process. For example, while the drive to continually produce smaller transistors is an industry imperative, smaller components on each chip also mean more likely defects as well as higher resistance to the heartbeat of electrical current flowing through each component. With higher resistance comes performance penalties and heat buildup.

"Multicore processors are the next wave of increasing the performance and efficiency of the processor itself," says Yurii Vlasov, a staff researcher at IBM's Thomas J. Watson Laboratory. "But if you look five or 10 or 20 years ahead, the problem is not just to decrease size and to cram more transistors into a single area, but to enable communications between the cores at a level where it will not be a bottleneck as it is now.

"What's happening now is that the performance of especially high-performance chips is not only limited by the amount of transistors we can put in, but also by the amount of signals we can transfer between cores or to another chip nearby. And that bottleneck will be even more severe when they increase the number of cores."

Vlasov is among the IBM researchers working on silicon nanophotonics interconnect technology. In some ways, this effort might be among the most easily understood of the cutting-edge research projects. The principles and appeal of nanophotonics closely parallel those of optics technologies already deployed in telecommunications networks or in advanced preproduction development stages.

Just as telecommunications carriers replaced copper wires with optical fiber to exploit fiber's speed and capacity advantage over copper, Vlasov and his colleagues are exploring whether nanophotonics will enable production-capable data transmission at faster speeds than metallic interconnects on a chip-sized scale.

"We are trying to build a toolbox of components that can be further integrated into our own chip network," Vlasov says. They want to add another, optical-network layer to a silicon chip. For that, he says, "we need to explore how small the optical components—switches, modulator, waveguide—can be, how scalable they are, and if they can be integrated on silicon."

Vlasov says silicon nanophotonics, if feasible, won't be included in production processors until 2015 to 2020, when the industry is expected to be producing 22-nanometer transistors.

The recent interconnect research at HP Labs might bear fruit much sooner, according to Williams.

In a paper (http://www.iop.org/EJ/abstract/-search=15831911.2/0957-4484/18/3/035204) published in the Institute of Physics' Nanotechnology, Williams and colleague Gregory Snider proposed a nanowire crossbar interconnect structure that sits above the chip's logic layer. In this way, Williams says, the essential property of Moore's law—the doubling of capacity for constant cost—can be obtained simply by adding more logic to the existing chip. Because the interconnect technology is no longer taking up space on that plane, there's no need to shrink the transistor.

"We would, in principle, ride off whatever advances people make in shrinking transistors by using hafnium oxide or whatever else you have to do," he says. "But by being more efficient in the interconnect, we're showing the possibility of advancing three, four, or maybe even five generations without ever shrinking the transistor."

One advantage of this approach, Williams says, is that manufacturers can capitalize on both current and future technologies. By 2010, he says, the crossbar interconnect could be theoretically feasible for 30-nanometer technology but also compatible with 45-nanometer transistors, which he envisions will be a fully mature standard by then. Williams predicts dramatic advances from the crossbar technology and architectures: an eightfold improvement in logic density over current state-of-the-art chips, while doubling operating speed and power efficiency.

IBM researchers in Zürich have turned to biological circulation principles to more efficiently cool processors (http://www.zurich.ibm.com/news/06/cooling.html). The researchers have demonstrated great improvements in both cooling efficiency and product protection by using tree-like hierarchical branched channels in a chip cap interface between the chip and the insulating paste separating the chip from a system's cooling medium. When pressure is applied to the interface, the paste spreads much more evenly and the pressure remains uniform across the chip. This obtains the right uniformity with about half the pressure (and a corresponding decreased danger of damaging the chip) and tenfold better heat transport through the interface.

Bruno Michel, manager of the advanced-thermal-packaging research group in Zürich, says the chip cap might be ready for production within one to two years. Meanwhile, his group is already investigating likely successors to the chip cap. One candidate is a liquid cooling technology called direct-jet impingement. It squirts water onto the back of the chip and sucks it off again in a perfectly closed system using an array of up to 50,000 tiny nozzles and a complicated tree-like branched return architecture.

"In one of the next generations, there is no way around liquid cooling," Michel says.

And, ultimately, experts say, there's no way around abandoning silicon transistors. One material envisioned as a likely successor is the carbon nanotube. In 1993, researchers at IBM and NEC (where Sumio Iijima discovered the nanotube two years earlier) found they could produce graphite (carbon) tubes in a single atomic layer. The nanotube properties could prove ideal for transistors. They're stronger than carbon steel and thermally stable at extremely high temperatures, enabling a wide range of manufacturing modalities. They also possess the unique ability to act as a conductor, semiconductor, or insulator—depending on how they're fabricated. This property has even led to speculation that someday nanoelectronics might be completely carbon-based.

IBM nanotube researcher Joerg Appenzeller says carbon's promise is counterbalanced by the difficulty in envisioning both an overall manufacturing model and specific fabrication problems with carbon.

"Everything the industry has done successfully up to now has been from the top down—you had a big chunk of material, and you shaped it the way you liked it," Appenzeller says. "The big challenge is to throw this overboard and perfect bottom-up self-assembly."

This ability to perfect uniform growth of carbon nanotubes still bedevils the industry; research-grade nanotubes can cost from US$350 to $2,000 per gram, depending on purity.

"We would love to take a substrate, prepattern a catalyst, and then have the tubes all grown and hopefully end up with the kind of alignment and positioning that you need to make a workable product," Appenzeller says. "There are a number of growth experts out there who have shown truly amazing stuff, but I would say it will be a couple of years from now before we can use that the way we want for the electronics."

Appenzeller and his colleagues, however, demonstrated in 2006 a workable circuit (http://www.sciencemag.org/cgi/content/abstract/ 311/5768/1735?rss=1%5D%5B%5BBREVIA%5D)on a single carbon nanotube in a ring oscillator.

"We tried to envision the results, based on what we know best—the circuit architectures silicon has shown and proved—of what would happen if we could sprinkle in nanotubes there and not change everything, but keep the circuit architecture in the same place," he says. "It's a hybrid approach, a real-life example that that idea works, that I don't have to reinvent everything."

HP Labs' Williams says he believes the continued advances in research show that the computing age has barely begun. "Just in terms of performance, we have a long, long way to go. There's no physical or fundamental physics reason why what we now know as Moore's law can't be going on well into the middle of this century."