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20-Bit RISC and DSP System Design in an FPGA
PrePrint
ISSN: 1521-9615
Amit Tomar, LNCT, bhopal, bhopal
Rita Jain, LNCT, bhopal, bhopal
These days most microprocessor and microcontroller designs are based on RISC core and many operation such as Discrete Cosine transform (DCT) , Inverse DCT, Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT) are performed by DSP system. This paper represent the design of a Reduced Instruction Set Computer (RISC) and Digital Signal Processor (DSP) system described using VHDL and implement in a Field Programmable Logic Array (FPGA). This RISC is a 20 bit processor.
Citation:
Amit Tomar, Rita Jain, "20-Bit RISC and DSP System Design in an FPGA," Computing in Science and Engineering, 21 Feb. 2013. IEEE computer Society Digital Library. IEEE Computer Society, <http://doi.ieeecomputersociety.org/10.1109/MCSE.2013.20>
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