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20-Bit RISC and DSP System Design in an FPGA
PrePrint
ISSN: 1521-9615
| ASCII Text | x | ||
| Amit Tomar, Rita Jain, "20-Bit RISC and DSP System Design in an FPGA," Computing in Science and Engineering, vol. 99, no. 1, pp. 1, , 5555. | |||
| BibTex | x | ||
| @article{ 10.1109/MCSE.2013.20, author = {Amit Tomar and Rita Jain}, title = {20-Bit RISC and DSP System Design in an FPGA}, journal ={Computing in Science and Engineering}, volume = {99}, number = {1}, issn = {1521-9615}, year = {5555}, pages = {1}, doi = {http://doi.ieeecomputersociety.org/10.1109/MCSE.2013.20}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - Computing in Science and Engineering TI - 20-Bit RISC and DSP System Design in an FPGA IS - 1 SN - 1521-9615 SP EP EPD - 1 A1 - Amit Tomar, A1 - Rita Jain, PY - 5555 VL - 99 JA - Computing in Science and Engineering ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MCSE.2013.20
These days most microprocessor and microcontroller designs are based on RISC core and many operation such as Discrete Cosine transform (DCT) , Inverse DCT, Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT) are performed by DSP system. This paper represent the design of a Reduced Instruction Set Computer (RISC) and Digital Signal Processor (DSP) system described using VHDL and implement in a Field Programmable Logic Array (FPGA). This RISC is a 20 bit processor.
Citation:
Amit Tomar, Rita Jain, "20-Bit RISC and DSP System Design in an FPGA," Computing in Science and Engineering, 21 Feb. 2013. IEEE computer Society Digital Library. IEEE Computer Society, <http://doi.ieeecomputersociety.org/10.1109/MCSE.2013.20>
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